# semiconductor market for AI data center chips Market Research Report - United States

**Generated on:** 2026-09-23 07:50:13.571161  
**Industry:** semiconductor market for AI data center chips  
**Geography:** United States  
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# US AI Data-Center Chips: Growth Meets Infrastructure Limits

## Executive Summary

- **Market Size Depends On Scope**: Omdia's narrow compute-silicon definition grows from **$123B in 2024** to **$207B in 2025** and **$286B by 2030**. Gartner's broader AI data-center ecosystem, including memory and supporting silicon, represents **36.5% of a $1.555T global semiconductor market in 2026**, implying about **$568B**. The large difference is definitional, not an error -> use both estimates as planning boundaries and do not present a single false-precision US market value [4][7].
- **US Hyperscalers Set The Demand Curve**: Amazon plans **$220B** of 2026 capital spending, Alphabet guides to **$195B-$205B**, and Meta to **$130B-$145B**; Microsoft spent **$41B** in its latest quarter. These totals include buildings and power infrastructure, not only chips, but they establish an exceptional demand floor -> suppliers should align capacity to contracted deployments rather than headline capex alone [17][9][8][10].
- **NVIDIA Remains The System-Level Leader**: NVIDIA produced **$89B** of fiscal Q2 2027 data-center revenue, including **$49B** from hyperscalers and **$40B** from AI clouds, industrial and enterprise customers -> challengers must compete with its integrated compute, networking, systems and software stack, not merely GPU specifications [5].
- **AMD And Broadcom Validate A Multi-Vendor Market**: AMD's Q2 2026 data-center revenue reached **$6.7B**, up **107% YoY**; Broadcom's Q1 FY2026 AI revenue reached **$8.4B**, up **106%**, with **$10.7B** expected in Q2 -> buyers can improve negotiating leverage and supply resilience through qualification of alternate GPUs and custom accelerators [6][2].
- **Custom Silicon Is Structural, Not A Temporary Experiment**: Omdia finds custom ASICs gaining traction, while Google's TPU7x became generally available and AWS positions Trainium around production-scale cost per token -> hyperscalers should reserve custom chips for stable, high-volume workloads while retaining GPUs for flexibility and frontier models [4][20][24].
- **Memory And Packaging Capture More Value**: Gartner expects memory to represent **54%** of 2026 semiconductor revenue, while NVIDIA says extreme memory pricing is exceeding prior expectations -> procurement strategies must secure HBM, substrates and packaging at the system level, not treat accelerators as stand-alone parts [7][5].
- **Power Becomes The Deployment Gate**: US data centers consumed about **176 TWh**, or **4.4%** of national electricity, in 2023; DOE projects **325-580 TWh**, or **6.7%-12%**, by 2028 -> site power, interconnection and cooling readiness should precede chip purchase commitments [3].
- **The Downside Is An ROI And Utilization Shock**: Amazon's trailing-12-month free cash flow moved to a **$7.6B outflow** as AI-related property and equipment purchases rose, while overinvestment can strand data-center assets -> track utilization, AI revenue conversion and free cash flow alongside orders and capex [11][19].

## Market Boundary And Size: Two Lenses Prevent False Precision

This report defines the US market by where demand is specified, purchased and deployed, while recognizing that the physical supply chain remains global. It includes accelerators, custom AI ASICs, server CPUs, HBM and other data-center memory, networking and interconnect silicon, DPUs and SmartNICs, power-management devices, advanced packaging and foundry capacity. It excludes complete servers, construction, utilities and software except where those categories explain chip demand.

| Market layer | Included products | Primary suppliers | Demand mechanism |
|---|---|---|---|
| Accelerated compute | GPUs, merchant AI accelerators, FPGAs | NVIDIA, AMD, Intel and emerging specialists | Training, inference and high-performance computing |
| Custom compute | TPU, Trainium, Maia, MTIA and customer-specific XPUs | Google, Amazon, Microsoft and Meta, with Broadcom and Marvell design support | Lower cost and power for stable hyperscale workloads |
| Host compute | x86 and Arm server CPUs | AMD, Intel, NVIDIA and cloud-designed CPUs | Data preparation, orchestration and general cloud workloads |
| Memory | HBM, DRAM, NAND and enterprise storage | SK hynix, Micron and Samsung | Model size, bandwidth and checkpointing requirements |
| Connectivity | Ethernet and InfiniBand switches, NICs, DPUs, optical DSPs and retimers | Broadcom, NVIDIA, Marvell and others | Scale-up and scale-out cluster performance |
| Manufacturing | Leading-edge wafers, CoWoS-class packaging and substrates | TSMC, Samsung, Intel Foundry, OSATs and substrate vendors | Converts chip designs and HBM into deployable systems |

Two credible forecasts illustrate why category definition matters. Omdia measures processors used for AI, including GPUs, ASICs, ASSPs, FPGAs and CPUs with integral AI acceleration. It estimates **$123B** shipped in 2024, **$207B** in 2025 and **$286B** in 2030. The implied 2025-2030 CAGR is about **6.7%**, a major deceleration from the roughly **67%** growth projected for 2025 [4].

Gartner uses a much broader ecosystem view. It forecasts total worldwide semiconductor revenue of **$1.555T in 2026**, with the AI data-center ecosystem accounting for **36.5%**, rising above **53% by 2030**. Multiplying those published 2026 figures yields an implied ecosystem value near **$568B**, but that includes memory and supporting silicon excluded from Omdia's narrower compute estimate [7].

There is no standardized, public US-only revenue series across all these layers. Allocating the global market using data-center count, corporate headquarters or chip shipment destination would each produce a different answer. The decision-ready conclusion is therefore a range: use Omdia for the addressable compute-processor pool, Gartner for the full semiconductor-content pool, and US hyperscaler capex as the most current geographic demand indicator.

## Hyperscaler Capex Converts Into Silicon Demand, But Not One For One

| Buyer | Current spending signal | What it implies | Important caveat |
|---|---:|---|---|
| Amazon | **$220B** 2026 capex plan | Very large AWS compute, memory and infrastructure demand | Higher memory costs contributed to the increase [17] |
| Alphabet | **$195B-$205B** 2026 guidance; **$44.9B** in Q2 | Accelerated delivery of AI capacity | Capex includes servers, data centers and networking, not just semiconductors [8] |
| Meta | **$130B-$145B** 2026 guidance; **$31.08B** in Q2 | Internal training and recommendation infrastructure remains a major demand source | Includes finance-lease principal and non-chip property and equipment [9] |
| Microsoft | **$41B** latest-quarter capex | Azure continues adding AI and cloud capacity | A quarterly figure should not be directly added to annual guidance [10] |

Amazon, Alphabet and Meta alone guide to **$545B-$570B** of 2026 capital expenditures. The mechanism connecting this spending to semiconductors is straightforward: accelerated clusters require compute devices, HBM, host CPUs, NICs, switches and optical links before they can produce usable tokens. Larger clusters also raise memory and network content per accelerator, so semiconductor value can grow faster than the number of installed processors.

However, capex is not chip revenue. It also funds land, buildings, cooling, electrical equipment and long-lived network infrastructure. Alphabet's disclosure is instructive: its Q2 spending was concentrated in technical infrastructure, split between servers and data-center or networking assets. This is a useful conversion framework, but it still does not reveal the semiconductor share inside servers [8].

Amazon provides the clearest warning against equating spending with attractive returns. Its trailing-12-month free cash flow fell from an **$18.2B inflow** to a **$7.6B outflow**, primarily because net property and equipment purchases increased by **$66.1B**, mainly reflecting AI investment [11]. This does not prove overbuilding, but it raises the hurdle for future cloud revenue, utilization and margin.

**Case study - Alphabet's mixed merchant and custom strategy.** Alphabet raises capex while simultaneously commercializing its own TPU platform. TPU7x became generally available in March 2026, and by June, standard Compute Engine APIs could create and manage TPU virtual machines and slices [24]. The mechanism is portfolio optimization: GPUs preserve compatibility and flexibility, while TPUs target workloads where Google controls enough software and volume to justify specialization.

For suppliers, the action is to map design wins to powered sites, committed HBM and packaging slots, and customer deployment schedules. For buyers, the action is to separate infrastructure budgets into compute, memory, network and facility components, then evaluate cost per trained model or served token rather than purchase price alone.

## Competitive Landscape Across Compute, Memory And Connectivity

| Company | Position in the US market | Latest relevant metric | Competitive advantage | Principal risk |
|---|---|---:|---|---|
| NVIDIA | GPU, system, networking and software leader | **$89.0B** data-center revenue in Q2 FY2027 | Integrated systems, rapid product cadence and broad developer ecosystem | Supply bottlenecks, memory inflation and export exposure [5] |
| AMD | Merchant GPU and server-CPU challenger | **$6.7B** data-center revenue in Q2 2026, **+107% YoY** | EPYC installed base, open software alternative and expanding Instinct portfolio | Execution against NVIDIA's system and software stack [6] |
| Broadcom | Custom XPU and Ethernet-enabling silicon | **$8.4B** Q1 FY2026 AI revenue, **+106% YoY** | Hyperscaler co-design and network silicon breadth | Customer concentration and outsourced supply chain [2] |
| Micron | US-headquartered HBM, DRAM and NAND supplier | **$13.77B** cloud-memory plus **$11.52B** core-data-center revenue in the quarter ended May 28, 2026 | Domestic strategic importance and exposure to rising memory content | Memory cyclicality and capital intensity [1] |
| Marvell | Custom compute, interconnect and optical silicon | **$2.17B** data-center revenue in Q3 2026 | Custom ASIC and connectivity exposure | Scale and customer-program timing [1] |
| Intel | Server CPU, accelerator and domestic foundry participant | **$6.26B** Data Center and AI revenue in Q2 FY2026 | x86 installed base and US manufacturing option | Accelerator competitiveness and foundry execution [1] |
| SK hynix | Leading HBM supplier | HBM4 mass shipments began in Q2 2026 | HBM process leadership and close accelerator integration | Korea concentration and difficult capacity scaling [15] |
| TSMC | Critical leading-edge foundry and packaging partner | Three planned Arizona fabs backed by a **$6.6B** direct CHIPS award | Process technology, yield and advanced packaging ecosystem | Taiwan concentration and long fab ramp cycles [22] |

**Case study - NVIDIA changes the unit of competition.** NVIDIA's **$96B** fiscal Q2 2027 total revenue more than doubled YoY, while data-center revenue reached **$89B**. Hyperscalers contributed **$49B**, but AI-cloud, industrial and enterprise customers contributed another **$40B**, showing that growth is broadening beyond the largest cloud operators [5]. NVIDIA also began Vera Rubin production shipments and reported purchase orders from major hyperscalers, AI clouds and system OEMs [5].

The mechanism is system-level integration. Compute performance alone is insufficient at cluster scale; networking, memory bandwidth, rack design, compilers and libraries determine delivered throughput and time to deployment. NVIDIA therefore captures value across more of the bill of materials, while its competitors often enter through one layer.

AMD's counter-position is credible but narrower. Its data-center business more than doubled YoY, supported by EPYC CPUs and Instinct GPUs, and the MI400 family targets both training and inference [6]. Broadcom attacks from a different direction: it helps hyperscalers build custom accelerators and supplies networking silicon. This does not necessarily displace all GPUs; it can displace selected high-volume workloads while expanding the surrounding connectivity market.

The practical implication is portfolio competition rather than winner-take-all replacement. NVIDIA remains the default for frontier flexibility; AMD is the principal merchant alternative; Broadcom and Marvell monetize custom designs and connectivity; Micron and Asian memory suppliers capture bandwidth growth; and Intel remains relevant through host CPUs and US manufacturing policy.

## GPUs Versus Custom ASICs: The Make-Or-Buy Decision

The relevant framework is total cost of ownership, or TCO, combined with a make-or-buy decision. Buyers should compare silicon price, utilization, power, networking, software migration, engineering labor and workload longevity. An ASIC can be superior per token yet economically inferior if the model architecture changes before development costs are amortized.

| Decision dimension | Merchant GPU | Custom ASIC |
|---|---|---|
| Best fit | Frontier training, changing models, broad third-party software | Stable, repetitive, high-volume training or inference |
| Time to deployment | Faster because hardware and software are already available | Slower due to architecture, verification and software work |
| Flexibility | High | Lower and workload-specific |
| Unit economics at scale | Carries vendor and flexibility premium | Can reduce cost and power after sufficient utilization |
| Strategic benefit | Access to a broad ecosystem and newest capabilities | Supply diversification, bargaining leverage and platform differentiation |
| Main failure mode | Vendor concentration and high acquisition cost | Design delay, low utilization or workload obsolescence |

Omdia expects alternatives to GPUs to gain traction and explicitly includes custom ASICs such as Google's TPUs in that shift [4]. Google demonstrates the commercialization path: TPU7x is generally available, and customers can manage TPUs through standard Compute Engine and managed-instance-group APIs. That reduces operational friction and turns an internal accelerator into a cloud product [24].

AWS follows the same logic with Trainium, which it describes as a purpose-built AI chip focused on production-scale cost per token [20]. Microsoft targets inference with Maia, while Meta develops MTIA for internal recommendation and inference workloads. These programs matter even if they never replace GPUs broadly: they redirect selected volumes, pressure merchant pricing and increase demand for design partners, foundries, HBM and networking.

Broadcom is the clearest public-market beneficiary of this transition. Its Q1 FY2026 AI revenue grew **106%** to **$8.4B**, driven by custom accelerators and AI networking, and management expected **$10.7B** in Q2 [2]. Custom silicon therefore shifts value rather than simply destroying it: accelerator value may move away from a merchant GPU vendor, while design, foundry, packaging, memory and interconnect suppliers still benefit.

The recommended architecture is heterogeneous. Reserve merchant GPUs for frontier models, variable demand and external developer compatibility. Deploy custom chips for stable internal workloads with high utilization and a multi-year software commitment. Maintain portability at the model, compiler and orchestration layers so that chip specialization does not become an irreversible platform lock-in.

## HBM, Packaging, Networking And Power Become Binding Constraints

| Constraint | Evidence | Mechanism | Strategic response |
|---|---|---|---|
| HBM and memory | Memory is forecast to represent **54%** of 2026 semiconductor revenue; DRAM revenue is forecast up **246.6%** [7] | Larger models require more bandwidth and capacity per accelerator | Contract memory with accelerators; qualify multiple suppliers |
| Advanced packaging | NVIDIA expects supply to remain a bottleneck through at least FY2028 [5] | GPUs, chiplets and HBM must be integrated with high yield | Reserve packaging, substrates and test capacity together |
| Networking and optics | Gartner identifies rising CPU, network, power-management and optical content as clusters scale [7] | Distributed training loses value if communication cannot keep accelerators utilized | Measure cluster-level throughput, not chip peak performance |
| Electricity | DOE projects **325-580 TWh** of US data-center demand by 2028 [3] | A chip order creates no revenue-producing compute without energized capacity | Tie procurement milestones to interconnection and generation readiness |
| Local infrastructure | RAND estimates about **82 GW** of net additional reliable US capacity by 2030, but completion is uncertain and geographically uneven [23] | Generation may be distant from load or delayed by interconnection and transmission | Diversify regions and contract firm power early |

Memory is no longer a secondary component. Gartner attributes much of 2026 semiconductor growth to memory pricing and AI-server content, forecasting **$837B** of memory revenue in 2026. It expects HBM and higher memory content per server to support growth beyond 2027 [7]. NVIDIA reinforces the near-term pressure, stating that memory-price increases exceeded its prior expectations and were headed higher [5].

**Case study - HBM4 turns memory into a roadmap dependency.** SK hynix began HBM4 mass shipments in Q2 2026 and planned a second-half ramp [15]. Unlike commodity memory procurement, HBM must be qualified alongside accelerator designs and advanced packaging. A delay in any one element can strand the others, which raises the value of long-term agreements but also creates take-or-pay and inventory risk if end demand changes.

Packaging and network design create similar system effects. As accelerators become faster, underprovisioned network fabrics reduce utilization, while advanced packaging determines whether compute dies and HBM can operate as one reliable module. The market therefore expands beyond GPUs into switches, NICs, optical DSPs, retimers and packaging equipment.

Power is the final gate. DOE estimates US data-center electricity use could reach **6.7%-12%** of total national consumption by 2028, up from **4.4%** in 2023 [3]. The national total can obscure local scarcity: AI loads are large and geographically concentrated, while planned power projects have uncertain completion rates [23]. Water availability, cooling design and permitting add location-specific constraints. The commercial lesson is simple: powered, cooled and networked capacity should be the denominator for semiconductor demand forecasts, not announced data-center square footage.

## US Policy Improves Resilience But Does Not Eliminate Global Dependence

| Recipient | Final direct CHIPS support | Strategic contribution | Limitation |
|---|---:|---|---|
| Intel | Up to **$7.865B** | Domestic leading-edge manufacturing across several US projects | Execution, yield and customer adoption remain commercial risks [21] |
| TSMC Arizona | Up to **$6.6B**, plus up to **$5B** in proposed loans | Three Phoenix fabs, more than **$65B** planned investment and an A16 commitment | Parent technology, much packaging capacity and ecosystem depth remain centered in Asia [22] |
| Micron | Up to **$6.165B** | Expands US memory manufacturing capacity | HBM supply still depends on complex global equipment, materials and packaging chains [18] |
| Samsung | Up to **$4.745B** | Adds another leading-edge manufacturing source in the United States | Ramp timing and product qualification matter more than nominal wafer capacity [25] |

The CHIPS program addresses the largest structural weakness in the US market: US companies lead much accelerator and cloud-system design, but leading-edge fabrication, HBM and advanced packaging remain concentrated in Taiwan and South Korea. The awards improve geographic diversity and create a potential domestic path for foundry and memory supply.

The mechanism is slow, however. Fabs require years to build, equip, qualify and ramp. Nominal wafer capacity also does not guarantee HBM, substrates, advanced packaging, test capacity or competitive yields. Policy therefore reduces tail risk rather than making the US supply chain self-sufficient.

Export controls create the opposite force: they protect national-security objectives but reduce addressable markets and complicate product planning. Current BIS guidance requires licenses for specified advanced-computing exports involving entities headquartered in designated Country Group D:5 jurisdictions or Macau, including certain ultimate-parent relationships [14]. AMD's Q2 2025 comparison included an **$800M** inventory and related charge tied to US controls on MI308 products, illustrating a direct financial transmission channel [6]. NVIDIA excludes China data-center compute revenue from its forward outlook [5].

This produces a policy tension. Domestic subsidies encourage capacity expansion just as export restrictions can remove demand and force region-specific products. Suppliers should incorporate licensing, end-user diligence and product reconfiguration into roadmap economics. Buyers should qualify geographically diverse sources but recognize that switching foundries or packaging flows requires redesign and requalification, not a simple purchase-order change.

The best policy metric is not dollars awarded. It is qualified output from US fabs and packaging lines, delivered at competitive yield and connected to domestic memory, substrates, workforce and equipment support.

## Risk Scenarios And Decision Triggers

| Scenario | Observable triggers | Market effect | Recommended action |
|---|---|---|---|
| Upside: supply-constrained expansion | High cloud backlog, sustained accelerator orders, powered sites and continued HBM tightness | Compute, memory, networking and packaging revenue remain elevated | Secure multi-year capacity, but preserve price and volume reopeners |
| Base: growth normalizes and mix broadens | Omdia's forecast deceleration, custom ASIC share gains and inference expansion | GPUs continue growing more slowly while ASIC, networking and memory capture more mix | Build heterogeneous architectures and diversify qualified suppliers |
| Downside: utilization and ROI reset | Slower AI revenue conversion, capex cuts, lower cluster utilization and negative free cash flow | Order pushouts, memory-price reversal and inventory correction | Stage deployments, avoid speculative inventory and stress-test customer concentration |
| Disruption: policy or supply shock | New export restrictions, Taiwan disruption, packaging outage or power delay | Product redesign, lost regional revenue and delayed installations | Hold geographic and architectural alternatives before the shock occurs |

**Demand and ROI risk.** The industry's circularity is a central concern: cloud operators buy chips to offer AI capacity, while model developers and enterprises must generate enough revenue to pay for that capacity. McKinsey warns that overinvestment can strand assets and estimates a multitrillion-dollar global data-center capital requirement [19]. Amazon's **$7.6B** trailing free-cash-flow outflow shows how quickly infrastructure spending can exceed internal cash generation, even before proving that the investment is uneconomic [11].

**Concentration risk.** A small number of hyperscalers account for much advanced-chip demand, while a small number of foundries, HBM suppliers and packaging providers enable supply. Broadcom explicitly identifies loss of significant customers, demand-timing fluctuations, contract-manufacturing dependence and limited suppliers as material uncertainties [2]. Volume commitments reduce supply risk but can magnify a downturn.

**Technology risk.** Faster model efficiency does not automatically reduce compute demand; lower cost can expand usage. Conversely, it can alter the winning hardware mix. Inference favors cost, power and latency, while frontier training rewards flexibility and scale. A supplier can therefore be correct about AI growth but wrong about which architecture captures it.

**Financial risk.** Memory inflation, power equipment and construction costs can raise cluster costs faster than AI-service prices. NVIDIA already reports stronger-than-expected memory pricing [5]. Contract structures should separate unavoidable input-cost pass-through from supplier margin expansion.

The most useful dashboard combines: accelerator and HBM lead times; packaging utilization; cloud backlog; AI service revenue; cluster utilization; capex-to-operating-cash-flow; free cash flow; powered megawatts; interconnection dates; and customer concentration. No single metric distinguishes a healthy buildout from overcapacity.

## Synthesis: Four Strategies, Different Moats And Failure Modes

| Strategy | Value-creation mechanism | Scope and time horizon | Main trade-off | Current evidence |
|---|---|---|---|---|
| NVIDIA integrated platform | Captures compute, networking, systems and software value | Broadest workload scope; immediate deployment and rapid annual cadence | Premium cost and supplier concentration | **$89B** quarterly data-center revenue and broad hyperscale plus enterprise demand [5] |
| AMD merchant alternative | Combines competitive GPUs with EPYC host CPUs | Broad workloads; medium-term ecosystem build | Lower ecosystem scale but greater buyer leverage | **$6.7B** quarterly data-center revenue, up **107% YoY** [6] |
| Hyperscaler custom silicon | Optimizes silicon and software for recurring internal workloads | Narrower workloads; multi-year development and amortization | Better potential TCO versus lower flexibility | TPU availability, Trainium positioning and Omdia's custom-ASIC traction [4][20][24] |
| Enabling infrastructure | Monetizes every architecture through memory, foundry, packaging and connectivity | Architecture-agnostic; tied to total cluster scale | Capital intensity, cyclicality and supply concentration | Memory reaches **54%** of 2026 semiconductor revenue under Gartner's forecast [7] |

Three non-obvious conclusions follow.

First, custom ASIC growth does not imply the collapse of merchant GPUs. GPUs maximize option value for rapidly changing models; ASICs maximize economics after workloads stabilize. The likely end state is heterogeneous, with custom silicon absorbing predictable internal workloads while GPUs remain central to frontier development and external cloud compatibility.

Second, the most defensible opportunities may migrate away from the accelerator die. Every architecture requires HBM, packaging, network fabrics, power management and optical connectivity. These enabling layers benefit from aggregate compute growth, although memory cyclicality and supplier concentration make them far from risk-free.

Third, semiconductor supply and data-center deployment are becoming inseparable. DOE's power range is wide because site readiness, grid capacity and project completion are uncertain [3][23]. The relevant market is not chips ordered, but chips that can be packaged, networked, powered, cooled and utilized.

**For chip suppliers:** prioritize contracted workloads, secure HBM and packaging jointly, and disclose customer concentration and capacity commitments. **For cloud buyers:** use a portfolio of merchant and custom accelerators, measure TCO per useful token, and connect orders to powered-site milestones. **For investors:** monitor cash conversion, utilization and backlog quality rather than capex announcements alone. **For policymakers:** measure qualified domestic output, packaging and workforce readiness, not only announced fab investment.

The base strategic judgment is continued US market expansion with slower percentage growth, broader architecture mix and rising value in memory, connectivity and manufacturing. The largest opportunity is the full AI system. The largest risk is building any one layer faster than the rest of the system can absorb it.

## References

1. *Fiscal.ai /v2/company/segments-and-kpis*. https://fiscal.ai
2. *Broadcom Inc. Announces First Quarter Fiscal Year 2026 Financial Results and Quarterly Dividend | Broadcom Inc.*. https://investors.broadcom.com/news-releases/news-release-details/broadcom-inc-announces-first-quarter-fiscal-year-2026-financial
3. *DOE Releases New Report Evaluating Increase in Electricity Demand from Data Centers | Department of Energy*. https://www.energy.gov/articles/doe-releases-new-report-evaluating-increase-electricity-demand-data-centers
4. *New Omdia forecast: AI data center chip market to hit $286bn, growth likely peaking as custom ASICs gain ground*. https://omdia.tech.informa.com/pr/2025/aug/ai-data-center-chip-market-to-hit-286bn-growth-likely-peaking-as-custom-asics-gain-ground
5. *NVIDIA Corp.*. https://s201.q4cdn.com/141608511/files/content_files/TRANSCRIPT_-NVIDIA-Corp-NVDA-US-Q2-2027-Earnings-Call-26-August-2026-5_00-PM-ET.pdf
6. *AMD Reports Second Quarter 2026 Financial Results :: Advanced Micro Devices, Inc. (AMD)*. https://ir.amd.com/news-events/press-releases/detail/1295/amd-reports-second-quarter-2026-financial-results
7. *Gartner Forecasts Worldwide Semiconductor Revenue to Reach $1.6 Trillion in 2026*. https://www.gartner.com/en/newsroom/press-releases/2026-08-24-gartner-forecasts-worldwide-semiconductor-revenue-to-reach-1-trillion-dollars-in-2026
8. *2026_Q2_Earnings_Transcript*. https://s206.q4cdn.com/479360582/files/doc_events/2026/Jul/22/2026_Q2_Earnings_Transcript.pdf
9. [
	Meta - Meta Reports Second Quarter 2026 Results
](https://investor.atmeta.com/investor-news/press-release-details/2026/Meta-Reports-Second-Quarter-2026-Results/default.aspx)
10. *Microsoft Fiscal Year 2026 Fourth Quarter Earnings Conference Call*. https://www.microsoft.com/en-us/investor/events/fy-2026/earnings-fy-2026-q4
11. [
	Amazon.com, Inc. - Amazon.com Announces Second Quarter Results
](https://ir.aboutamazon.com/news-release/news-release-details/2026/Amazon-com-Announces-Second-Quarter-Results/)
12. *TSMC 2026 Q2 Quarterly Results - Taiwan Semiconductor ...*. https://investor.tsmc.com/english/quarterly-results/2026/q2
13. *Maia 200: The AI accelerator built for inference*. https://blogs.microsoft.com/blog/2026/01/26/maia-200-the-ai-accelerator-built-for-inference
14. *Guidance Regarding Enforcement of License Requirements for Advanced Computing Items for Entities Headquartered in Country Group D:5 and Macau [May*. https://www.bis.gov/media/documents/bis-guidance-may-31-2026.pdf?hl=zh-CN
15. *SK hynix Announces 2Q26 Financial Results – SK hynix Newsroom*. https://news.skhynix.com/en/q2-2026-business-results/
16. *Broadcom Showcases Industry-Leading Solutions for Scaling AI Infrastructure at OFC 2026*. https://www.broadcom.com/company/news/product-releases/64036
17. *Amazon increases AI infrastructure spending to $220bn ...*. https://www.ft.com/content/fddc42a9-4c57-4689-abde-75bbe79622e9?syn-25a6b1a6=1
18. *Department of Commerce Awards CHIPS Incentives to Micron ...*. https://www.commerce.gov/news/press-releases/2024/12/department-commerce-awards-chips-incentives-micron-idaho-and-new-york
19. *The cost of compute: A $7 trillion race to scale data centers*. https://www.mckinsey.com/industries/technology-media-and-telecommunications/our-insights/the-cost-of-compute-a-7-trillion-dollar-race-to-scale-data-centers
20. *AI Accelerator - AWS Trainium*. https://aws.amazon.com/ai/machine-learning/trainium/
21. *Biden-Harris Administration Announces CHIPS Incentives Award with Intel to Advance U.S. Leading-Edge Chip Capacity and Create Tens of Thousands of Jobs | U.S. Department of Commerce*. https://www.commerce.gov/news/press-releases/2024/11/biden-harris-administration-announces-chips-incentives-award-intel
22. *Biden-Harris Administration Announces CHIPS Incentives Award with TSMC Arizona to Secure U.S. Leadership in Advanced Semiconductor Technology | U.S. Department of Commerce*. https://www.commerce.gov/news/press-releases/2024/11/biden-harris-administration-announces-chips-incentives-award-tsmc
23. *How Much More Power Can the U.S. Grid Provide for AI? Projections and Policy Implications for 2030*. https://www.rand.org/content/dam/rand/pubs/research_briefs/RBA3800/RBA3845-1/RAND_RBA3845-1.pdf
24. *Cloud TPU release notes  |  Google Cloud Documentation*. https://docs.cloud.google.com/tpu/docs/release-notes
25. *Biden-Harris Administration Announces CHIPS Incentives Award with Samsung Electronics to Solidify U.S. Leadership in Leading-Edge Semiconductor Production | U.S. Department of Commerce*. https://www.commerce.gov/news/press-releases/2024/12/biden-harris-administration-announces-chips-incentives-award-samsung